The present subject matter relates to a clock alignment training operation which is required in a high-speed semiconductor memory device, and more particularly, to a circuit which can reduce time taken for a clock alignment training operation in a semiconductor memory device.
In a system including a plurality of semiconductor memory devices, the semiconductor memory devices are used for storing data. When a data processor such as a memory control unit (MCU) requests data, the semiconductor memory device outputs data corresponding to an address input from the data processor requesting data, or stores data provided from the corresponding data processor in a position corresponding to the address.
To this end, a high-speed memory device, which is developed recently, is designed to input/output two data between a rising edge and a falling edge of an external system clock and to input/output two data between the falling edge and a next rising edge of the external system clock. In short, the high-speed memory device is designed to input/output four data in one cycle of a system clock.
However, since the system clock is merely represented as two states, i.e., logic high or logic low, a data clock having two times higher frequency than that of the system clock is required for inputting/outputting four data in one cycle. That is, a dedicated clock for input/output of data is essentially required.
Accordingly, when an address and a command are received/transmitted, the high-speed semiconductor memory device uses the system clock as a reference clock. When data are input/output, the high-speed semiconductor memory device performs control in order for the data clock to have frequency two times higher than that of the system clock using the data clock as the reference clock.
That is, the high-speed semiconductor memory device repeats two cycles of the data clock for one cycle of the system clock, and inputs/outputs data at a rising edge and falling edge of the data clock respectively. Therefore, the high-speed semiconductor memory device can input/output four data for one cycle of the system clock.
In this way, the high-speed semiconductor memory device exchanges data using two clocks having different frequencies for performing a read or write operation, as opposed to a conventional Double Data Rate (DDR) synchronous memory device which uses one system clock as a reference clock for performing a read or write operation.
However, when a phase of the system clock and a phase of the data clock are not aligned, a reference for transfer of an operation command and an address and a reference for transfer of data are not aligned. This signifies that the high-speed semiconductor memory device cannot normally operate.
Therefore, to normally operate the high-speed semiconductor memory device, an interface training operation between the high-speed semiconductor memory device and a data process device must be performed at an initial operation.
Herein, the interface training means that an interface for transferring commands, addresses and data is trained in order to operate at an optimal time before a normal operation between the semiconductor memory device and the data process device is performed.
The interface training is divided into clock alignment training (WCK2CK training), read training, and write training. In the clock alignment training (WCK2CK training), the data clock and the system clock are aligned.
FIG. 1 is a block diagram of a circuit performing the clock alignment training in accordance with a conventional technology.
First, in the basic principle of the clock alignment training, the high-speed semiconductor memory device receives an address signal and a command signal from an external controller on the basis of the system clock HCK, and outputs data stored in the semiconductor memory device to the external controller on the basis of the data clock WCK as described above.
Accordingly, when there is a phase difference between the system clock HCK and the data clock WCK, the data stored in the semiconductor memory device reach the external controller more quickly or more slowly by a time corresponding to the phase difference.
Consequently, the clock alignment training is an operation in which the high-speed semiconductor memory device detects a phase difference between the data clock WCK and the system clock HCK applied from the external controller at an initial operation and transmits the detection result to the external controller, and thus reduces the phase difference between the system clock HCK and the data clock WCK.
That is, in the circuit for performing the clock alignment training in accordance with the conventional technology illustrated in FIG. 1, the circuit receives a data clock OUT_WCK and a system clock OUT_HCK from the external controller, buffers the data clock OUT_WCK and the system clock OUT_HCK to output a buffered data clock WCK and a buffered system clock HCK, detects the phase difference between the data clock WCK and the system clock HCK, and transmits the detection result to the external controller.
Referring to FIG. 1, the circuit includes a clock inputting unit 100 receiving the system clock OUT_HCK for synchronizing an input time of the address signal and an input time of the command signal and the data clock OUT_WCK, which a has higher frequency than that of the system clock OUT_HCK, for synchronizing an input time of the data signal from the external controller, and outputs the buffered system clock HCK and the buffered data clock WCK. The circuit further includes a clock dividing unit 120 dividing a frequency of the data clock WCK to generate a data division clock DIV_WCK in order for the data division clock DIV_WCK to have the same frequency as that of the system clock HCK, a phase detecting unit 140 detecting a phase difference between the system clock HCK and the data division clock DIV_WCK and generating a detection signal DET_SIG corresponding to the detection result, and a signal transmitting unit 160 transmitting the detection signal DET_SIG as a training information signal TRAINING_INFO_SIG to the external controller.
FIG. 2 is a timing diagram illustrating an operation waveform of the conventional circuit of FIG. 1 performing the clock alignment training.
Referring to FIG. 2, although a frequency of the data clock WCK, which is input to the circuit for performing the clock alignment training in accordance with the conventional technology from the external controller, is higher than that of the system clock HCK, it can be seen that a frequency of the data division clock DIV_WCK output from the clock dividing unit 120 is the same as that of the system clock HCK because the clock dividing unit 120 changes a frequency of the data clock WCK in order for the frequency of the data clock WCK to be the same as that of the system clock HCK.
Moreover, referring to FIG. 2, clock edges are not synchronized with one another at the moment {circle around (1)} before the performing of the clock alignment training operation. That is, the phase of the data clock WCK and the phase of the data division clock DIV_WCK are not synchronized with the phase of the system clock HCK at the moment {circle around (1)} before the performing of the clock alignment training operation.
Still referring to FIG. 2, the circuit changes the phase of the data clock WCK and the phase of the data division clock DIV_WCK in a state where the phase of the system clock HCK is constant in order to synchronize the phase of the data clock WCK and the phase of the data division clock DIV_WCK with the phase of the system clock HCK at moments {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)} after the starting of the clock alignment training operation.
At this point, the phase of the data clock WCK and the phase of the data division clock DIV_WCK are changed according to a logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) transmitted to the external controller by the signal transmitting unit 160. That is, since the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is continuously a logic low state, the external controller gradually changes the phase of the data clock WCK and the phase of the data division clock DIV_WCK and applies the data clock WCK and the data division clock DIV_WCK to the circuit for performing the clock alignment training.
Then, at the moment {circle around (6)} when the phase of the data clock WCK and the phase of the data division clock DIV_WCK are synchronized with the phase of the system clock HCK, the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is changed from a logic low state into a logic high state. In a section {circle around (7)} when the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is continuously maintained as the logic high, the phases of the data clock WCK and the data division clock DIV_WCK are no longer changed. That is, since there is a state where the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is changed into the logic high, the external controller makes the phase of the data clock WCK and the phase of the data division clock DIV_WCK constant and applies the data clock WCK and the data division clock DIV_WCK to the circuit for performing the clock alignment training.
As a result, it can be seen that the circuit for performing the clock alignment training continuously compares the phase of the data clock WCK with the phase of the system clock HCK through the phase detecting unit 140 and transfers the comparison result, i.e., the training information signal DET_SIG (TRAINING_INFO_SIG) to the external controller until the phases of the data clock WCK and the data division clock DIV_WCK input from the external controller are synchronized with the phase of the system clock HCK through the clock alignment training operation.
The reason why the circuit for performing the clock alignment training is included in a semiconductor memory device is to synchronize the phase of the data clock WCK with the phase of the system clock HCK by performing the clock alignment training operation at a power supply time when a power supply voltage is firstly applied to the semiconductor memory device, i.e., a power up time.
However, the circuit must synchronize the phase of the data clock WCK with the system clock HCK by performing the clock alignment training operation even at an exit time when it exits from an operation mode such as a power down mode for supporting the reduction of the power consumption of the semiconductor memory device. The reason for synchoronization of the data clock WCK with the system clock HCK via the clock alignment training operation is as follows. In a state where the circuit enters an operation mode such as the power down mode, since data are not input/output in the semiconductor memory device, only the system clock HCK is input to the semiconductor memory device and the data clock WCK is not input to the semiconductor memory device. Thus, the phase of the data clock WCK may not be synchronized with the phase of the system clock HCK due to the change of the phase of the data clock WCK in a case that the circuit exits from the operation mode like the power down mode and the data clock WCK is again input to the semiconductor memory device.
At this point, in an entry/exit process of the operation mode such as the power down mode, since a jitter component occurs in the data clock WCK due to noise, the phase of the data clock WCK may be changed. However, the probability of occurrence of the phase change is very low, and very short time is taken for synchronizing the phase of the data clock WCK with the phase of the system clock HCK through the clock alignment training operation even though the phase change occurs. Accordingly, the phase change of the data clock WCK cannot exert influence on the total operations of the semiconductor memory device.
Above all, among the elements of the circuit for performing the clock alignment training operation of FIG. 1, the clock dividing unit 120 is turned on/off and a clock division time is changed in an entry/exit process of the operation mode such as the power down mode, and thus the phase of the data clock WCK can be inverted. In a case that the phase inversion occurs, since the phase of the data clock WCK must be changed by more than ½tCK for again synchronizing the phase of the data clock WCK with the phase of the system clock HCK through the clock alignment training operation, it takes very long time for the phase change, and, consequently, the total operations of the semiconductor memory device can largely be delayed.
These problems can be serious as the frequency of the system clock HCK and the frequency of the data clock WCK decrease.